1. Field of the Invention
This invention relates to the field of switching power converters, and particularly to techniques which mitigate crosstalk between the channels of a multi-channel switching power converter.
2. Description of the Related Art
Multi-channel switching power converters, in which two or more switching converters are arrayed in parallel, have become increasingly popular. A two-channel converter, for example, refers to a configuration in which there are two complete converter control circuits on one IC, each of which drives its own inductor, power switch, and synchronous rectifier (depending on the particular converter topology). The two channels are essentially independent, and can be set to provide two different output voltages if desired.
An example of such an arrangement is shown in FIG. 1a, which illustrates a two-channel buck converter. The first channel 10 consists of a switching means 12 which includes a switching transistor MN1 and a second switching transistor MN2 operated as a synchronous rectifier, connected together at a node 14. An output inductor L1 is connected between node 14 and an output node OUT1, and an output capacitor C1 is connected between OUT1 and ground. A controller 16 provides driving signals DRVH1 and DRVL1 to MN1 and MN2, respectively, as needed to provide a desired output voltage at OUT1. The second channel 20 is similarly arranged, with a switching means 22 consisting of transistors MN3 and MN4 connected together at a node 24, output inductor L2, output capacitor C2, and a controller 26 which provides driving signals DRVH2 and DRVL2 to MN3 and MN4, respectively, as needed to provide a desired output voltage at output node OUT2.
A problem can arise in arrangements of this sort. The controllers of some switching power converters operate by performing a signal sampling operation at a predetermined time in the switching cycle. Unfortunately, the sampled signal in the channel of interest can be corrupted if the other channel undergoes a transition during the sampling event. For the purposes of this discussion, the channel of interest will be referred to as the ‘Victim’ channel and the other channel will be referred to as the ‘Aggressor’ channel. One particular event that can give rise to this problem is when the Aggressor channel switches from a ‘drive high’ (DRVH) condition (synchronous rectifier MN2 is off, power switch MN1 on) to a DRVL condition (power switch MN1 off, synchronous rectifier MN2 on) at the same time or approximately 50-100 ns before the Victim channel is sampling a critical signal—e.g., the Vds voltage of synchronous rectifier MN2. This may occur, for example, in a converter using a control scheme which employs an emulated current mode architecture in which the current is measured based on the estimated Rds(on) of the synchronous rectifier (MN2, MN4). At the end of the DRVL condition, a voltage representing this current is saved on a sample-and-hold capacitor to serve as the starting point for the ramp voltage used in the control scheme, which is an emulation of the inductor current. It is this sample-and-hold operation that is sensitive to noise from the other channel.
This scenario is illustrated in FIG. 1b. In this example, a channel's high-side switch (MN1, MN3) is ‘on’ when DRVH is high, and its low-side switch (MN2, MN4) is ‘on’ when DRVL is high. Here, the Aggressor channel is CH. 2 and the Victim channel is CH. 1. As part of each channel's control scheme, a sampling operation is performed once per switching cycle, just prior to a transition between a DRVL condition and a DRVH condition, in a window of time δ. If the Aggressor channel switches from a DRVH condition to a DRVL condition during time δ, as it does in FIG. 1b, the resulting crosstalk can corrupt the sampled information and cause jittery response in the Victim channel.
Two channel switching power converters such as those shown in FIG. 1a are typically driven with clocks that are 180° out-of-phase to reduce input voltage ripple. As a result, the crosstalk problem described above is most evident when the Aggressor channel operates at approximately 50% duty cycle. For this reason, the problem is often described (in two-channel switch mode controllers and regulators) as the 50% duty cycle problem.
The 50% duty cycle problem has proven to be particularly vexing. One approach that has been tried involves making the sensing amplifier—used to amplify and condition the Vds voltage of the synchronous rectifier prior to sampling the voltage onto a holding capacitor—impervious to common-mode noise that can give rise to the crosstalk problem described above. Unfortunately, no method of filtering or other means of rejecting the common-mode noise has proven to be practical. Over-filtering by placing a low-pass filter in the signal path on the IC has also been tried, but this ultimately reduced the transient response of the controller, causing it to fail other required performance objectives.